1. Field of the Invention
The present invention relates to a data processing apparatus, and more particularly to a memory access control unit for controlling access to a memory unit consisting of a plurality of memory banks.
In a memory unit consisting of a plurality of memory banks, any individual memory bank is in a busy state as long as it is being accessed. Once a memory bank enters into a busy state, it can permit no other access until it is released from that busy state. The memory access control unit according to the present invention is intended to manage the busy state of each memory and to judge whether or not any subsequent access to the memory can be permitted.
2. Description of the Prior Art
Units of this kind according to the prior art for managing the busy state of memory units include, for instance, what is disclosed in the U.S. Pat. No. 4,435,765 granted on Mar. 6, 1984. This prior art unit controls access to a vector register consisting of a plurality of banks in a vector processor. For this control, the unit has a bank slot reserve control section in its access start control circuit to keep track of the busy or unbusy state of each bank. In this bank slot reserve control section according to the prior art, flip-flops (F/F's) of one bit for each bank are provided in one-to-one correspondence. Accordingly, F/F's of as many bits as the banks are required, and this configuration is difficult to realize where the number of banks is greater than a certain limit. When this bank slot reserve control section is to be applied to a memory unit having a plurality of memory ports, the busy state has to be checked over a plurality of memory ports, so that a large amount of complex hardware should be provided.
An object of the present invention is to provide a memory access control unit capable of readily controlling access to a memory unit having a plurality of memory ports, each of which is to be connected to a plurality of banks.